JIF Component Library¶
The built-in JIF component library provides style-based shapes for diagrams
generated by pyadi-jif. Enable it by passing library="jif" to
d2.compile().
import d2
code = """
direction: right
adc: ADC { class: adc }
ddc: DDC { class: ddc }
framer: JESD204 Framer { class: jesd204framer }
adc -> ddc -> framer
"""
svg = d2.compile(code, library="jif")
The JIF library is designed to match pyadi-jif Node.ntype values. When
pyadi-jif draws a node with Node("ADC", ntype="adc"), it emits
class: adc and compiles with library="jif".
Use the JIF library to create:
Converter datapaths — ADC, DAC, DDC, DUC, and crossbar blocks
JESD links — framers, deframers, serializer/deserializer blocks, and IP layers
Clock trees — dividers, PLLs, charge pumps, loop filters, and VCOs
FPGA paths — PHY, transceiver, CPLL/QPLL, decoder, and transport blocks
System Overview Styling¶
The light and dark JIF themes share semantic containers and signal styles for readable system-level diagrams. Both palettes use amber for clocks, magenta dashed lines for SYSREF, cyan for JESD data, violet for references, green for converters, and cyan-blue FPGA containers. The light variant uses pale tinted surfaces while the dark variant uses a navy technical canvas. Color is paired with line width or dash style so signal types remain distinguishable without relying on color alone.
code = """
direction: right
ref: 125 MHz reference { class: input }
clock: Clock tree { class: jif-container-clock }
converter: AD9084 RX { class: jif-container-converter }
fpga: Xilinx VCU118 { class: jif-container-fpga }
ref -> clock: 125 MHz { class: jif-signal-reference }
clock -> converter: Device clock · 20 GHz { class: jif-signal-clock }
clock -> fpga: SYSREF · 25 MHz { class: jif-signal-sysref }
converter -> fpga: JESD204C · 8 lanes × 20.625 Gb/s { class: jif-signal-data }
"""
light_svg = d2.compile(code, library="jif", theme="light")
dark_svg = d2.compile(code, library="jif", theme="dark")