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IIO-Tools example:

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Python bindings example:

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hmc7044

Device Attributes

Name	Default value
mute_request
reseed_request
reset_dividers_request
sleep_request
sync_pin_mode
sync_pin_mode_available
sysref_request

Channel Attributes

CORE_CLK_RX

Name	sysfs filename	Examples
frequency	out_altvoltage0_CORE_CLK_RX_frequency	EX
phase	out_altvoltage0_CORE_CLK_RX_phase	EX

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CORE_CLK_RX_ALT

Name	sysfs filename	Examples
frequency	out_altvoltage10_CORE_CLK_RX_ALT_frequency	EX
phase	out_altvoltage10_CORE_CLK_RX_ALT_phase	EX

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FPGA_REFCLK2

Name	sysfs filename	Examples
frequency	out_altvoltage12_FPGA_REFCLK2_frequency	EX
phase	out_altvoltage12_FPGA_REFCLK2_phase	EX

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FPGA_SYSREF

Name	sysfs filename	Examples
frequency	out_altvoltage13_FPGA_SYSREF_frequency	EX
phase	out_altvoltage13_FPGA_SYSREF_phase	EX

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DEV_REFCLK

Name	sysfs filename	Examples
frequency	out_altvoltage2_DEV_REFCLK_frequency	EX
phase	out_altvoltage2_DEV_REFCLK_phase	EX

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DEV_SYSREF

Name	sysfs filename	Examples
frequency	out_altvoltage3_DEV_SYSREF_frequency	EX
phase	out_altvoltage3_DEV_SYSREF_phase	EX

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CORE_CLK_TX

Name	sysfs filename	Examples
frequency	out_altvoltage6_CORE_CLK_TX_frequency	EX
phase	out_altvoltage6_CORE_CLK_TX_phase	EX

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FPGA_REFCLK1

Name	sysfs filename	Examples
frequency	out_altvoltage8_FPGA_REFCLK1_frequency	EX
phase	out_altvoltage8_FPGA_REFCLK1_phase	EX

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